1. Field of the Invention
The present invention relates to the formation of wiring structures in integrated circuit devices. More particularly, the present invention relates to methods for improving process margins for forming wiring lines and for decreasing the spacing between wiring lines.
2. Description of the Related Art
Many highly integrated semiconductor circuits utilize multilevel wiring line structures for interconnecting regions within devices and for interconnecting one or more devices within the integrated circuits. Most often, the wiring lines of the multilevel interconnect structure are formed by conventional photolithographic techniques. For example, devices such as FETs, diodes or transistors are formed in and on the substrate to form an integrated circuit device and then a first level of insulating material is deposited over the device. A pattern of contact holes or vias is defined through the first level of insulating material and, at some point in the process, the contact holes are filled with a conducting material to define vertical interconnects through the first level of insulating material to contact appropriate portions of the devices on the surface of the substrate. A first metal layer that will be patterned to form a first level of wiring lines is deposited over the first level of insulating material and over the surface of the device. An etch mask is formed on the surface of the first metal layer that defines a pattern of openings above the wiring lines that will connect to various ones of the vertical interconnects. Generally, the etch mask is formed by providing a layer of photoresist on the surface of the first metal layer, exposing the layer of photoresist through an exposure mask and developing the photoresist to form the etch mask. Etching processes remove those portions of the first metal layer exposed by the etch mask, leaving behind the desired pattern of wiring lines. The etch mask is removed by washing. Processing continues to form additional levels of interconnects and wiring lines to complete the circuit.
A conventional multilevel wiring line structure and a method of making the structure are illustrated in FIGS. 1-3. FIG. 1 illustrates a semiconductor circuit at an intermediate step in the manufacturing process with a layer of dielectric material 12 covering a semiconductor substrate 10 where various devices have previously been formed. FIG. 2 illustrates a contact opening or via 14 formed above an underlying metal or polysilicon conductor or above a conductive region in the substrate 10. The first level wiring layer 16 includes material 15 located within the via 14 to contact the underlying conductor or conductive region. The wiring layer 16 is patterned and anisotropically etched to define individual wiring lines 18 on the surface of the dielectric layer. Often, the pattern is formed so that the anisotropic etching takes place near the edges of contact vias. Ideally, the individual wiring lines 18 will appear as illustrated in FIG. 3, with the via 14 centered under the wiring line and filled with wiring line material 15.
Dielectric layers for wiring line isolation are often formed by chemical vapor deposition (CVD) processes, which deposit a material onto a surface by transporting gaseous precursors to the surface and causing the precursors to react at the surface. A common CVD process for gap filling is plasma-enhanced chemical vapor deposition (PECVD), which uses a plasma to impart energy to the reactant gases. It has been observed that dielectric material builds up on the upper corner portions of wiring lines when deposition methods such as PECVD are used to fill small gaps between the wiring lines. The build-up of oxide can cause undesirable cavities or voids to form within the dielectric material between the wiring lines. As illustrated in FIG. 4, an oxide layer 20 deposited using PECVD TEOS over substrate 22, over the wiring lines 24 and within the gaps 26 between wiring lines 24, will build up on the upper corner regions of the wiring lines 24 and form overhang regions 28. As the deposition proceeds and the oxide material accumulates on the overhang regions 28, adjacent overhang regions 28 will contact each other and close off voids 30 between the wiring lines 24, as illustrated in FIG. 5. These voids 30 may create channels that run parallel to adjacent metal lines 24 along their length. Subsequent planarization processes may uncover or partially open the voids 30 and materials such as polishing chemicals or polymerized etch byproducts may become trapped in the voids 30. Material trapped in the voids 30 may be difficult to remove, and subsequent processing steps may then exhibit reduced yields due to contamination from the materials trapped in the voids 30. As a result, it is desirable to completely fill gaps between wiring lines to prevent the formation of voids where contaminants may accumulate.
In addition, as devices are made smaller and smaller, it is desirable for the wiring lines to be spaced very closely together in order to increase the wiring line density in the device. A limiting factor in such applications is the resolution limit of the lithography method used for patterning the wiring lines. It would be desirable to form wiring lines which are spaced apart a distance less than the lithography resolution limit.